1. Field of the Invention
This invention relates generally to a method for manufacturing a semiconductor device and more particularly to a method of etching an electrode or wiring material as formed on or above an ultra-thin gate dielectric film.
2. Description of the Related Art
The transistors used in logic circuits and/or system LSIs are required to offer ever higher performance. Therefore, the thickness of the gate dielectric films are currently designed to be not more than 3 nm, and there is development work to make the film thinner, not more than 2 nm. In addition, the length of a gate electrode has been developed to scale down to not more than 0.1 xcexcm (100 nm)
An etching process using a method for manufacturing such minute gate electrodes is required to achieve a high accuracy of finished dimension with respect to gate electrodes while at the same time controlling damage to the thin gate dielectric film. In responding to such demands, several proposals have been made as to high-selectivity etching methods for etching gate electrode material while preventing etching of a gate dielectric film associated therewith.
FIG. 11 is a flow diagram showing conventional method of manufacturing a semiconductor device, which has been disclosed in J. Vac. Sci. Technol., B18 (1), 156, wherein S1 designates processing start-up, S2 denotes a main etching process step (etching of a gate electrode), S3 indicates termination point detection (detection of a residual film thickness of 30 nm of amorphous Si), S4 shows an overetching process step, and S5 is processing completion, respectively. Disclosed here is a semiconductor device manufacturing method which combines, with respect to amorphous Si gate electrode etching, the main etching of a gate electrode using a gas containing therein chlorine (Cl2), hydrogen bromide (HBr) and oxygen(O2) and the overetching of a gate dielectric film using a gas containing HBr and O2 for permitting etching of gate electrode material while preventing etching of the gate dielectric film to thereby realize high selectivity etching.
The method of manufacturing the semiconductor device employs etching apparatus such as a helicon plasma RIE apparatus or the like for etching with respect to a semiconductor substrate 1 which comprises a gate dielectric film 2 with a thickness of 1.8 nm, an amorphous Si film 3 with a thickness of 150 nm and a mask 4 that is formed of a 50-nm thick TEOS oxide film as shown in FIG. 12, thereby making a gate electrode 31 as shown in FIG. 13.
In such semiconductor device manufacturing method, the etching of gate electrode 3xe2x80x2 (main etching) is performed by introducing the mixture gas containing chlorine (Cl2), hydrogen bromide (HBr) and oxygen (O2) into the above-noted helicon plasma RIE apparatus for production of a reactive plasma under the condition that RF bias power is set at 150W to thereby etch a portion or portions of the amorphous Si 3 at which the mask 4 is not formed. Additionally at this time, an ellipsometry film thickness monitor as installed within a chamber is used to monitor a residual film thickness of the amorphous Si 3; when the residual film thickness of amorphous Si 3 becomes 30 nm through progression of etching, changeover is done to specific etching condition of high selectivity (etching rate ratio of gate electrode layer/gate dielectric film layer isxe2x89xa6100) which prevents the gate dielectric film 2 from being cut away (referred to as overetching process hereinafter). At the overetching process step, any amorphous Si presently residing on the gate dielectric film is subjected to etching for a predetermined length of time period under the condition that RF bias power of helicon plasma RIE apparatus is at 60W while using a mixture gas (O2 addition amount≈14%) of HBr (50 sccm) and O2 (8 sccm).
FIG. 13 is a cross-sectional view of the gate electrode 3xe2x80x2 after completion of etching up to the termination point judgment (a time point for detection of a residual film thickness of 30 nm of amorphous Si 3) by use of the semiconductor device manufacturing method concerned, wherein numeral 5 indicates amorphous silicon with a thickness of 30 nm as left after execution of the main etching. In addition, FIG. 14 is a sectional view of gate electrode 3xe2x80x2 after having performed etching processing up to the overetching by using the semiconductor device manufacturing method, wherein 6 denotes deposition matter being attached to gate electrode sidewalls, such as SiBrxOy.
The conventional gate electrode is etched by the method described above and has a tapered sectional shape such as shown in FIG. 13. Because stable control of the taper angles of this shape is difficult, the gate electrode varies from the design size. The deviation in gate size has been a problem in semiconductor device manufacturing and fabrication methods. Additionally for the future, in the manufacture of certain devices with gate length Lg less than 0.1 xcexcm, it is readily presumed that this gate size deviation can reduce device production yields. Further, in the case of forming a gate electrode on an ultrathin gate dielectric film (Tox less than 3 nm), there is also a problem that setting of a relatively stronger overetching condition for suppression of the O2 addition amount of overetchingxe2x80x94that is, low in selectivityxe2x80x94when attempting to obtain an anisotropic etching shape would result in the gate dielectric film also being etched, which leads to occurrence of xe2x80x9cgo-throughxe2x80x9d portions 7 in the gate oxide film such as shown in FIG. 15.
Accordingly, it is an object of the present invention to provide a semiconductor device manufacturing method producing an anisotropic etching shape during etching of a Si-contained electrode and/or wiring lead material on or above a dielectric film and further capable of etching of electrodes and/or wiring leads without associated creation of go-through portions of the dielectric film even in cases where an underlying dielectric film is an ultrathin film.
A method of manufacturing a semiconductor device according to the present invention includes a main etching step of applying etching treatment to an electrode or wiring material being formed on or above a dielectric film as provided at a semiconductor substrate surface to thereby expose the dielectric film, a first overetching step of etching away, after the main etching step, etching residues of the electrode or the wiring material having failed to be etched during etching treatment of the main etching step by etching utilizing a first mixture gas comprising a halogen gas and an additive gas having an effect for suppression of etching of the dielectric film by the halogen gas, and a second overetching step of etching away, after the first overetching step, the etching residues by etching utilizing a second mixture gas comprising the halogen gas and the additive gas and having the additive gas amount of a ratio greater than the first mixture gas.
Further, according to the present invention, an additive gas is a gas selected from the group consisting of O2, N2, and a combination thereof.
Still further, according to the present invention, an additive gas in the first mixture gas is O2 with its addition amount of 5% or less.
Additionally, according to the present invention, a halogen gas is a gas selected from the group consisting of HBr, Cl2, HCl, HI and combinations thereof.
Additionally, according to the present invention, an electrode or wiring material contains Si.
Additionally, according to the present invention, an etching treatment at the main etching step utilizes a gas of HBr/O2/Cl based gas as a third mixture gas.
Additionally, according to the present invention, a time period of the overetching at the first overetching step is less than or equal to ⅓ of a time of overetching at the second overetching step.
Still additionally, according to the present invention, a semiconductor substrate is held at temperatures lower than or equal to 0xc2x0 C. at steps of the main etching step, the first overetching step and the second overetching step, respectively.